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CY28547
.......................Document #: 001-05103 Rev *B Page 7 of 24
3
0
SRC3
Allow control of SRC[T/C]3 with assertion of PCI_STP# or SW PCI_STP#
0 = Free running, 1 = Stopped with PCI_STP#
2
0
SRC2
Allow control of SRC[T/C]2 with assertion of PCI_STP# or SW PCI_STP#
0 = Free running, 1 = Stopped with PCI_STP#
1
0
SRC1
Allow control of SRC[T/C]1 with assertion of PCI_STP# or SW PCI_STP#
0 = Free running, 1 = Stopped with PCI_STP#
0
SRC0
Allow control of SRC[T/C]0 with assertion of PCI_STP# or SW PCI_STP#
0 = Free running, 1 = Stopped with PCI_STP#
Byte 5 Control Register 5
Bit
@Pup
Name
Description
7
0
LCD_96_100M[T/C]
LCD_96_100M[T/C] PWRDWN Drive Mode
0 = Driven in PWRDWN, 1 = Tri-state
6
0
DOT96[T/C]
DOT PWRDWN Drive Mode
0 = Driven in PWRDWN, 1 = Tri-state
5
0
RESERVED
RESERVED, Set = 0
4
0
RESERVED
RESERVED, Set = 0
3
0
PCIF0
Allow control of PCIF0 with assertion of SW and HW PCI_STP#
0 = Free running, 1 = Stopped with PCI_STP#
2
1
CPU[T/C]2
Allow control of CPU[T/C]2 with assertion of CPU_STP#
0 = Free running, 1 = Stopped with CPU_STP#
1
CPU[T/C]1
Allow control of CPU[T/C]1 with assertion of CPU_STP#
0 = Free running, 1 = Stopped with CPU_STP#
0
1
CPU[T/C]0
Allow control of CPU[T/C]0 with assertion of CPU_STP#
0 = Free running, 1 = Stopped with CPU_STP#
Byte 6 Control Register 6
Bit
@Pup
Name
Description
7
0
SRC[T/C]
SRC[T/C] Stop Drive Mode
0 = Driven when PCI_STP# asserted
1 = Tri-state when PCI_STP# asserted
6
0
CPU[T/C]2
CPU[T/C]2 Stop Drive Mode
0 = Driven when CPU_STP# asserted
1 = Tri-state when CPU_STP# asserted
5
0
CPU[T/C]1
CPU[T/C]1 Stop Drive Mode
0 = Driven when CPU_STP# asserted
1 = Tri-state when CPU_STP# asserted
4
0
CPU[T/C]0
CPU[T/C]0 Stop Drive Mode
0 = Driven when CPU_STP# asserted
1 = Tri-state when CPU_STP# asserted
3
0
SRC[T/C][9:1]
SRC[T/C][9:1] PWRDWN Drive Mode
0 = Driven when PD asserted
1 = Tri-state when PD asserted
2
0
CPU[T/C]2
CPU[T/C]2 PWRDWN Drive Mode
0 = Driven when PD asserted
1 = Tri-state when PD asserted
1
0
CPU[T/C]1
CPU[T/C]1 PWRDWN Drive Mode
0 = Driven when PD asserted
1 = Tri-state when PD asserted
0
CPU[T/C]0
CPU[T/C]0 PWRDWN Drive Mode
0 = Driven when PD asserted
1 = Tri-state when PD asserted
Byte 4 Control Register 4 (continued)
Bit
@Pup
Name
Description
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